The present invention relates to a synchronous data transfer system for an information processing system.
In conjunction with the synchronous data transfer system, there is known such an arrangement in which a reference clock is supplied to each of nodes of the system, wherein a given phase of the reference clock and a succeeding phase thereof which succeeds to the given phase are made use of in such a manner that a sender terminal or node starts to output the data in the given phase while a receiver terminal or node fetches the outputted data in the succeeding phase.
Further there is known such a synchronous data transfer system in which a reference clock is supplied to each of nodes provided in the system, wherein a given phase of the reference clock is utilized by a sender terminal or node for starting the output of data, while in a receiver terminal or node, edge of the data arrived is detected and the data is fetched on the basis of the detected edge.
Besides, there is also known such a synchronous data transfer system in which a reference clock is supplied to each of nodes provided in the system, wherein a sending terminal starts to output data in a given phase of the reference clock while outputting additionally a reception-dedicated clock which is delayed in consideration of the time for which the data remains valid in flip-flop circuits of the receiver terminal so that the receiver terminal or node fetches the data arrived on the basis of the reception-dedicated clock.
As the literature disclosing the relevant technologies, there may be mentioned U.S. Pat. No. 5,548,226. Further, reference may be made to "ELECTRONICS", July, 1993, pp. 5-6 and "NIKKEI ELECTRONICS", Sep. 27, 1993, pp. 269-290 as well.